Integrated circuits are typically fabricated by optical lithographic techniques, where energy beams transmit integrated circuit images or patterns on photomasks (equivalently, masks or reticles) to photosensitive resists on semiconductor wafer substrates, formed (equivalently, printed or transferred) as multiple layers of patterned materials overlain on the substrate. For each patterned layer formed on the substrate, there may be one or more masks used to form the printed patterns on the wafer. The patterns are typically expressed as polygons on the masks. However, the polygons of the mask transferred to or imaged on the wafer will be smoothed and distorted during the lithographic process of transferring the mask patterns to the wafer, due to a variety of optical effects, as is well-known in the art. Thus, it is desirable that the circuit designers take into account the characteristics of the lithographic process, as well as functional and performance requirements, while designing the circuit layout.
The process of manufacturing an integrated circuit using a lithographic process can be generally understood with reference to FIGS. 1A-1C.
Referring to FIG. 1A, during a circuit design process flow 10, a circuit designer will incorporate a set of design rules 11 for preparing polygons for the initial mask layout 15 that correspond to a desired circuit layout level. The rules 11 may be expressed as, for example, as look-up tables of two-dimensional criteria, and may include criteria related to requirements such as overlay tolerance, critical dimension (CD), minimum and maximum spacing between polygon shapes, etc. Optionally, the rules may be expressed in terms of tolerance bands around the desired design shapes. The designer will combine the requirements of the circuit logic 12 with the design rules 11, to arrive at an initial circuit layout 15, which typically comprises a two-dimensional layout of polygon shapes. Design rules 11 typically include tolerances and constraints and other criteria related to performance and electrical characteristics of circuit devices, as well as manufacturability rules, such as, for example, related to lithographic processes and overlay tolerances. An initial mask layout is typically assigned the same polygon layout as provided by the circuit layout 15. Typically, the initial mask layout 15 is written out as a data set which will be provided as input to the lithographers, for example, at the foundry or FAB. The process of writing out the mask layout data set is often referred to as tapeout 17, and the tapeout data set may be sent to the foundry as input to further analysis and modification 20 by the foundry lithographic engineers.
The circuit image on the photomask may not be reproduced precisely on the substrate, in part because of optical effects among transmitted and blocked energy passing through the photomask. Referring to FIG. 1B, prior to manufacturing the mask, the initial design layout 15 is typically modified to account for such optical effects. The process 20 of modifying the initial mask design 15 to form an actual, modified, mask layout 25 may include modifications by optical proximity correction (OPC) 29 and may optionally include resolution enhancement techniques (RET) 27. The process of modifying the mask layout is commonly referred to as data preparation (equivalently, “Data-Prep”) 20. Optical Proximity Correction (OPC) 29 has been employed as a key enabling resolution enhancement technique required to meet image size control requirements imposed by state-of-the-art integrated circuit product programs. OPC 29 is essentially the deliberate and proactive distortion of photomask patterns to compensate for systematic and stable errors. OPC is generally categorized as either rules-based or model-based. Rules-based OPC is done by determining the correctable imaging errors, calculating appropriate photomask compensations, and finally applying the calculated corrections directly to the photomask layout.
Model-based OPC (MBOPC) is based on the concept of capturing the imaging characteristics in a mathematical model 21 that represents the lithographic process, and calculating the expected on-wafer circuit image which would be projected by the mask pattern under investigation, comparing the simulated image contour placement to the edge placement of the original mask pattern and iteratively adjusting the mask patterns until a suitable match of the simulated image to the desired on-wafer target pattern 23, within specified tolerances and other mask layout rules 24, is obtained. The mask layout rules 24 may include manufacturability rules that relate to mask house requirements, which would typically not be applied during the design of the circuit layout (e.g. FIG. 1A). Note that typically, the on-wafer target pattern 23 has the same layout of polygons as the initial design layout 15, which represents what the designer intends to be printed on the wafer. While MBOPC results in greater fidelity in the printed image, the use of MBOPC requires significantly more computational resource than rules-based OPC.
Existing optical lithographic tools currently employ laser illumination at 193 nm wavelengths. For a given wavelength of illumination energy, the resolution of the lithographic process, or, in other words, the smallest dimension ρ that can be reliably imaged, is typically expressed by the Rayleigh scaling equation:
      ρ    =                  k        ⁢                                  ⁢        λ            NA        ,
where λ is the wavelength of the source light, NA (numerical aperture) is a measure of the amount of light that can be collected by the lens, and the so-called k-factor k represents aspects of the lithographic process other than wavelength or numerical aperture, such as resist properties or the use of enhanced masks. Typical k-factor values range from about 0.7 to 0.4. However, by using a variety of resolution enhancement technologies (RETs) such as sub-resolution assist features (SRAFs), alternating phase-shift masks (altPSM), the k-factor may be reduced to improve the resolution of the lithographic process. When RET is used along with and in addition to MBOPC, existing optical lithographic tools are being used to print ever smaller feature sizes, from 90 nm to 45 nm or smaller.
Model-based OPC, along with RET, as practiced today typically involves five primary polygon data sets:
an initial mask layout 15, which is used as input to MBOPC, which typically includes a polygon rendering of the circuit design 15 as laid out by the designers;
a RET layout, which is the initial input mask layout modified for resolution enhancement techniques (RET) such as assist features or alternating phase shapes;
a wafer target 23, which describes the desired on-wafer polygons, i.e. what is needed on the wafer to get the desired yield. Typically, the wafer target 23 is equivalent in layout to the initial mask or circuit design layout 15;
simulated contours, which are the predicted on-wafer polygons generated by convolving the mask layout with a mathematical model of the imaging process; and
the modified or interim mask layout 25, which is the output of an OPC iteration that describes the polygons to be placed on the photomask.
Model-based OPC is an iterative optimization process that involves:
generating simulated contours of the initial mask layout 15, typically modified to form a RET layout;
comparing the simulated contours to the wafer target 23;
adjusting the RET layout to compensate for offsets between the simulated contour and the wafer target 23—thereby generating the first estimate of the mask layout 25; and
repeating this process using the interim mask layout 25 from one iteration as the input for the next iteration.
This cycle is repeated until the offset between the simulated contour and the wafer target 23 is at an acceptable value, or until a maximum number of iterations is exhausted. The output of the final iteration becomes the actual mask layout 25 which is sent to the maskhouse.
A commonly applied simplification is that the initial input mask layout 15 is assumed to be equal to the wafer target 23.
The modified mask layout 25 may then be sent to a mask house and/or to the foundry or FAB, for fabrication. However, referring to FIG. 1C, before the mask is built, the modified mask layout 25 typically undergoes a further verification procedure 30, which verifies the mask manufacturability according to the requirements and capabilities of the mask house, and printability of the mask based on the detailed lithographic process of the specific FAB where the integrated circuit will be manufactured. The mask is checked for errors (Block 31) according to manufacturability and printability criteria that may be provided in a variety of forms, such as a detailed process model 33 and manufacturability and/or printability rules 34 provided by the FAB, and/or the mask house. The modified mask layout 25 is examined 31 for violations of the rules or for printability errors that may unacceptably increase the risk of yield failures for the specific lithographic process to be used. If the modified mask 25 passes the printability and manufacturability criteria (i.e., no errors are found in Block 37), then the mask may be built (Block 35). However, if mask errors are found, then the mask may have to be further modified as in the data prep procedure 20 of FIG. 1B, or possibly re-designed, as in procedure 10 of FIG. 1A.
More recently, it has been proposed that the mask layout be designed to ensure manufacturability and printability at the design stage. Referring to FIG. 2, this procedure, so-called design for manufacturing (DfM) 40, is a modification of the basic design flow 10 of FIG. 1A. Design rules 11 and circuit logic 12 are provided as input, as in a basic design flow 10 (see FIG. 1A), but the resulting mask layout 42, which may include RET shapes, is modified by a model-based layout optimization procedure 140. The model-based modification 140 takes as input a wafer target 43, along with specified tolerances and mask layout rules 41, and, using an initial process model 44, involves simulating an image 47 using the process model 44. As discussed above, the wafer target 43 is often has the same polygon layout as the initial circuit or mask design layout 15. The simulated contours are presented to the designers, thereby enabling them to adjust their layout shapes to obtain more favorable wafer shapes. This may be done, for example, by applying the RET to the layout 42 at hand, running OPC, and then using a process window model 44 (i.e. a model aware of process variations) to generate contour bands to present to the designer. Alternatively, the process model 44 may comprise a compact model which, with reasonable accuracy, describes the entire sequence of shape transforms from input layout, RET layout, mask layout, to simulated contour band. In most cases, the generated contours are evaluated for dimensional failures, i.e. layout verification 49, similar to the mask verification 30 (FIG. 1C), and error markers are presented to the designers to prompt a layout modification. If no errors are found (no errors in Block 48), then tapeout 45 of the modified layout may be performed and the dataset comprising the modified layout is then sent forward to the foundry and enters the data prep cycle 20 (FIG. 1B) as the input, initial mask layout 15 (FIG. 1B). Thus, desirably, the output of model-based layout optimization 140 that is sent to the foundry's RET/OPC analysis 20 should be exhibit fewer or no printability or manufacturability errors.
However, there are several drawbacks to this approach.
First, the development of lithographic and wafer etch processes and chip designs typically occurs concurrently over periods from about 6 months at minimum to 5 years or more. This development time frame makes it practically impossible to give designers accurate descriptions of the RET and OPC solutions as well as accurate process window models during the design of the chip. Having designers optimize layouts to inaccurate models and RET/OPC solutions while they are operating under the assumption that they have accurate insight into the patterning process can lead to catastrophic failures and would make manufacturability worst, not better.
Secondly, the primary customers for model-based layout optimization are fabless design houses which design chips to be manufactured at outside foundries. A key requirement for these fabless design houses is to maintain foundry portability (i.e. the ability to move their business from one foundry to a competing one) or even to outsource their product to multiple foundries at the same time. The success of model-based layout optimization is based on a detailed, accurate model of a particular foundry's RET/OPC and imaging solution, and thus fundamentally links the optimized layout to a specific foundry. Thus, performing a model-based layout optimization using the detailed process model for each individual foundry would be impractical. An alternative solution of using a ‘least common denominator’ model that describes the worst case printability failures for multiple foundries would be extremely conservative and would yield noncompetitive layout densities, which is of particular importance for multiple foundries collaborating or competing for fabless business.
Thirdly, when a designer manipulates the original layout based on simulation feedback, he/she is effectively introducing a new polygon set, i.e. the optimized layout no longer represents the original designer's intent, it represents what the designer had to do to the original intended layout to make it pass the model-based optimization. If this manipulated layout is introduced as the input layout to the RET/OPC flow the added polygon complexity and uncertainty over designer's intent, will introduce manufacturability risk and could have the exact opposite effect of what DfM is intending to achieve.
Modifications of OPC applications have been proposed that try to account for normal and unavoidable process variations by replacing the wafer target with a wafer target band and by replacing the simulated contours with simulated contour bands. The iterative optimization process remains the same, but the wafer target bands need to be generated either by the designer based on an understanding of shape tolerances required for circuit yield, or by the OPC tool from the input layout by applying tolerances communicated in the design rule manual. Such modifications to OPC have been termed process window OPC (PWOPC), and PWOPC has been proposed as a key component of a strategic design for manufacturability (DfM) solution.
However, implementation of PWOPC with DfM has the following difficulties: First, wafer target bands generated by the designer are completely unaware of the available process capability, i.e. the designers know what they would like, but can't tell what is reasonable to ask for in all layout situations. Secondly, wafer target bands generated by the OPC application are unaware of designer's needs, i.e. at this point, the process limitations are well known, but acceptable tolerances are not. Thirdly, the generation of the wafer target bands in either case is rules-based, i.e. a series of sizing operations and Booleans is performed to generate rectilinear approximations to the desired wafer target bands. Challenges in reliably manipulating layouts through complex rule sets drove the implementation of model-based OPC in the first place, and reestablishing a dependence on such rules-based operations would effectively be taking a step backwards and would introduce significant yield risk.
In view of the above, there is a need for a design for manufacturing solution that avoids the aforementioned difficulties, and provides a mask design that minimizes or avoids printability and/or manufacturability errors during mask verification at multiple foundries, and provides an efficient design process that is suitable for fab-less designs.